1. Field of the Invention
The present invention relates to integrated circuit design, and more specifically to a method and apparatus for reducing the effect of noise present along with an input signal when sampling the input signal.
2. Related Art
Sampling generally refers to capturing the strength of a signal at a time instance of interest. Capacitor circuits connected in parallel are often used to sample the voltage level of an input signal. One desirable feature of such sampling is that the effect of any noise present along with the input signal (on a path) be reduced/avoided when performing such sampling operations, as described with reference to an ADC.
FIG. 1 is a block diagram of a prior ADC used to illustrate the need to reduce the effect of any noise present along with an input when performing sampling operations. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S and digital error correction block 130. Each block is described below in further detail.
SHA 110 samples input signal received on path 134 and holds the voltage level of the sample for further processing. Each stage 120-1 through 120-S generates a sub-code corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. Digital error correction block 130 receives sub-codes from various stages, and generates a digital code (on path 146) corresponding to the sample received on path 134.
FIG. 2 further illustrates the logical operation of each stage (described with reference to stage 120-1 only, for conciseness) according to a prior approach. Stage 120-1 is shown containing flash ADC 250, digital to analog converter (DAC) 260, subtractor 270 and gain amplifier 280. Flash ADC 250 (an example of a quantizer) converts a sample of an analog signal received on path 111 into a corresponding P-bit sub-code provided on path 256. DAC 260 converts the sub-code received on path 256 into corresponding analog signal (Vdac) on path 267.
Subtractor 270 generates a residue signal as the difference of sample 111 (Vi) and the analog signal received on path 267 (Vdac). Gain amplifier 280 amplifies the residue signal (Vi-Vdac), which is provided on path 112 as an amplified residue signal. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the subsequent ADC stages.
Subtractor, DAC, and gain amplifier may be implemented using a capacitor network and an operational amplifier together operating as a switched capacitor amplifier. One prior switched capacitor amplifier implementing substracter 270, DAC 260, and gain amplifier 280 of stage 120-1 is described below with respect to FIGS. 3A and 3B.
FIG. 3A is an example switched capacitor amplifier illustrating combined implementation of DAC 260, subtractor 270, and gain amplifier 280 in one prior embodiment. FIG. 3B is a timing diagram depicting the sample and hold phases used in the operation of the circuit of FIG. 3A. The circuit diagram is shown containing op-amp 350, feedback capacitor 360, feedback switch 380 and circuit portions 301-1 through 301-2n. Circuit portions 301-1 is shown containing sampling capacitor 330-1, switch 310A-1, 310B-1 and 310C-1. The remaining circuit portions 310-2 through 310-2n may also contain similar components, and are not described in the interest of conciseness. Each component is described below in further details.
The circuit in FIG. 3A operates using two phase signals, shown as sampling phase clock 370 and hold phase clock 390. In the first phase (sampling phase 370) switches 310A-1 through 310A-2n are closed at time points 371 and the remaining switches 380, 310B-1 through 310B-2n, and 310C-1 through 310C-2n are kept open. As a result, each sampling (input) capacitor 330-1 through 330-2n is ideally charged (in duration between 371–372) to the voltage of input sample received on path 111 by time point 372.
In the second phase (between durations 391–392), feedback switch 380 is closed and switches 310A-1 through 310A-2n are kept open. Connections of switches 310B-1 through 310B-2n, and 310C-1 through 310C-2n are made such that the input terminals of each sampling capacitor 330-1 through 330-2n is connected either to Vref or to REFCM terminal, as determined from the output of flash ADC 250.
As a result, each of capacitors 330-1 through 330-2n transfers a charge proportional to the difference (residue) of input signal and the Vref or REFCM to feedback capacitor 360 (up to time point 392). The residue is amplified by op-amp 350 and provided as amplified residue signal to the next stage, as desired.
However, the input voltage provided on path 111 may contain various types of noise such as amplifier noise generated by SHA 110, noise generated by switches and other components, etc. Each sampling capacitor 330-1 through 330-2n samples the input signal along with the noise components present on path 111. The manner in which sampling capacitors sample both input signal and associated noise components is illustrated in FIG. 4.
FIG. 4 is a graph illustrating manner in which noise is sampled in addition to the analog input signal. The graph is shown containing sampling clock 370, input signal 430 and noise 450. Merely for illustration, the input signal and noise are shown as two separate signals. However, a cumulative signal (of input signal 430 and noise 450) is generally presented on path 111.
At time point 371, switches 310A-1 through 310A-2n are closed. As a result, the voltage on the sampling terminal of the capacitors (330-1 through 330-2n) starts increasing, and settles to the sampled input value (Vin) at time point 402. The input voltage remains a constant thereafter.
A noise signal (random) is shown varying randomly with respect to time and typically having zero mean value and a finite root mean square value. Due to the opening of switches at time point 372, each capacitor stores a (cumulative) voltage equaling the sum of settled input value (vin) and a noise value (with the root mean squared (RMS) value of the noise at the sampling time point).
Since each capacitor samples the noise between the same time points, the noise magnitudes sampled by the capacitors are correlated to each other (or same). As a result, the noise sampled by each sampling capacitor gets added at the input of the amplifier.
Accordingly, during hold phase (between time point 391 and 392), the amplified sum total of noise (sum of the noise sampled (N1) by all sampling capacitors 330-1 through 330-2n) is presented at the output of op-amp 350. Such noise propagation can cause an error in the residue signal and/or quantization, resulting in error in the sub-codes generated by various stages.
Therefore, what is needed is a method and apparatus for reducing the effect of noise present along with an input signal when sampling the input signal.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.